Enhancing Quality through Probabilistic On-Chip Test
Jennifer Dworak
Future integrated circuits will contain tens, hundreds, or possibly even a thousand cores per chip. However, the scaling techniques that will make this possible also make the underlying circuit fabric less reliable—leading to increased wearout and defects that cannot be detected at manufacturing. In response, the PI proposes fundamental research for generating new test sets on-chip to identify failing cores. The tests will be created “on-the-fly” and dynamically targeted to the most critical areas of a core. Some key portions of the proposed research involve the creation and verification of hardware monitors for determining which faults are most important for the user’s applications, the diagnostic use of online error detection hardware to pinpoint locations that caused previous failures, and the analysis and development of protocols to efficiently create and transport tests in a network-on-chip environment.
The great performance advantages of future multi-core devices will remain unrealized if the reliability of those devices cannot be trusted. The proposed research investigates critical tools for promoting that reliability. The integrated education plan provides research opportunities for students at multiple levels—from high school to graduate school—including students from underrepresented groups. In addition to recruiting undergraduates from Brown, the PI plans to work with the CRA-W DREU (Distributed Research Experiences for Undergraduates) program to host visiting female undergraduates for summer research. The PI will also recruit high school students from the Providence Public Schools, many of whom are members of underrepresented groups, for summer research through the Brown GK-12 program.
Link: http://www.nsf.gov/awardsearch/showAward.do?AwardNumber=0915302
Transcending the Thermal Management Challenges of Tera-Scale Computing
Sherief Reda
Elevated temperature is a major problem for the reliability, performance, power consumption, and packaging costs of integrated electronic devices.
Temperature is a main physical barrier limiting the performance benefits of future technologies that promise tera-scale integration. To meet the thermal management challenges of future many-core processors, this research program envisions a new class of intelligent dynamic thermal management systems that explore the vast search space of possible control parameter settings and decide the optimal temperature and performance targets. This research program also investigates new cooling system designs that enable the thermal management system to target directly hot spots at the micro scale. Directly targeting hot spots alleviates the thermal constraints on performance.
The proposed research program will lead to transformative solutions and tools that address the fundamental thermal management challenges of computing systems and ensure their scalability. The proposed program will lead to the training of a diverse workforce of undergraduate and graduate students to be well prepared to deal with tomorrow’s thermal management challenges. The educational component of this program includes (1) research experiences for undergraduates; (2) integrated approach to entrepreneurship education with research; (3) hands-on training through the development of educational laboratories based on a state-of-the-art infrared camera; and (4) continuous education through the development of high-quality educational materials and an interactive technical Web site.